The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Nov. 09, 2007
Applicants:

Yolin Lih, San Jose, CA (US);

Ajay Bhatia, Santa Clara, CA (US);

Dennis Wendell, Sunnyvale, CA (US);

Jun Liu, Santa Clara, CA (US);

Daniel Fung, Santa Clara, CA (US);

Shyam Balasubramanian, Santa Clara, CA (US);

Inventors:

Yolin Lih, San Jose, CA (US);

Ajay Bhatia, Santa Clara, CA (US);

Dennis Wendell, Sunnyvale, CA (US);

Jun Liu, Santa Clara, CA (US);

Daniel Fung, Santa Clara, CA (US);

Shyam Balasubramanian, Santa Clara, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.


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