The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Aug. 03, 2005
Makoto Nakamura, Tokyo, JP;
Yohtaro Umeda, Tokyo, JP;
Jun Endou, Tokyo, JP;
Yuji Akatsu, Tokyo, JP;
Yuuki Imai, Tokyo, JP;
Masatoshi Tobayashi, Tokyo, JP;
Yoshikazu Urabe, Tokyo, JP;
Hatsushi Iizuka, Tokyo, JP;
Eiji Hyodo, Tokyo, JP;
Makoto Nakamura, Tokyo, JP;
Yohtaro Umeda, Tokyo, JP;
Jun Endou, Tokyo, JP;
Yuji Akatsu, Tokyo, JP;
Yuuki Imai, Tokyo, JP;
Masatoshi Tobayashi, Tokyo, JP;
Yoshikazu Urabe, Tokyo, JP;
Hatsushi Iizuka, Tokyo, JP;
Eiji Hyodo, Tokyo, JP;
Nippon Telephone and Telegraph Corporation, Tokyo, JP;
NTT Electronics Corporation, Tokyo, JP;
Abstract
A gain switching determination circuit () compares/determines a comparative input voltage (Vc) from an inter-stage buffer () with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.