The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Aug. 22, 2006
Applicants:

Jae Kyeong Jeong, Yongin-si, KR;

Hyun Soo Shin, Yongin-si, KR;

SE Yeoul Kwon, Yongin-si, KR;

Yeon Gon MO, Yongin-si, KR;

Inventors:

Jae Kyeong Jeong, Yongin-si, KR;

Hyun Soo Shin, Yongin-si, KR;

Se Yeoul Kwon, Yongin-si, KR;

Yeon Gon Mo, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor (TFT) and a method of manufacturing the same, and more particularly, a TFT for reducing leakage current and a method of manufacturing the same are provided. The TFT includes a flexible substrate, a diffusion preventing layer formed on the flexible substrate, a buffer layer formed of at least two insulated materials on the diffusion preventing layer, a semiconductor layer formed on a region of the buffer layer to include a channel layer and a source and drain region, a gate insulating layer formed on the buffer layer including the semiconductor layer, a gate electrode formed on the gate insulating layer in a region corresponding to the channel layer, an interlayer insulating layer formed on the gate insulating layer including the gate electrode, and source and drain electrodes formed in the interlayer insulating layer to include a predetermined contact hole that exposes at least a region of the source and drain region and to be connected to the source and drain region.


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