The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Apr. 29, 2008
Applicants:

Shenqing Fang, Fremont, CA (US);

Jihwan Choi, San Mateo, CA (US);

Connie Wang, Mountain View, CA (US);

Eunha Kim, Menlo Park, CA (US);

Inventors:

Shenqing Fang, Fremont, CA (US);

Jihwan Choi, San Mateo, CA (US);

Connie Wang, Mountain View, CA (US);

Eunha Kim, Menlo Park, CA (US);

Assignee:

Spansion, LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.


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