The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Mar. 31, 2008
Giri Nallapati, Austin, TX (US);
Sushama Davar, Austin, TX (US);
Robert E. Booth, Austin, TX (US);
Michael P. Woo, Austin, TX (US);
Mahbub M. Rashed, Austin, TX (US);
Giri Nallapati, Austin, TX (US);
Sushama Davar, Austin, TX (US);
Robert E. Booth, Austin, TX (US);
Michael P. Woo, Austin, TX (US);
Mahbub M. Rashed, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.