The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Dec. 09, 2005
Holger Haberla, Kranichfeld, DE;
Soeren Lohbrandt, Buessleben, DE;
Holger Haberla, Kranichfeld, DE;
Soeren Lohbrandt, Buessleben, DE;
X-FAB Semiconductor Foundries AG, Erfurt, DE;
Abstract
Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit () with inputs and outputs (), an embedded circuit () that is part of the whole circuit () and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs () of the whole circuit (); a test circuit () that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection () is provided which is used for separately supplying the embedded circuit () and the test circuit () independently of a supply voltage of the whole circuit () such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.