The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
May. 12, 2006
Bernard J. New, Carmel Valley, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
Jennifer Wong, Fremont, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
James M. Simkins, Park City, UT (US);
Bernard J. New, Carmel Valley, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
Jennifer Wong, Fremont, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
James M. Simkins, Park City, UT (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.