The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

Mar. 30, 2007
Applicants:

Gernot E. Günther, Endicott, NY (US);

Viktor Gyuris, Wappingers Falls, NY (US);

Kevin Anthony Pasnik, Cedar Park, TX (US);

Thomas John Tryt, Binghamton, NY (US);

John H. Westermann, Jr., Endicott, NY (US);

Inventors:

Gernot E. Günther, Endicott, NY (US);

Viktor Gyuris, Wappingers Falls, NY (US);

Kevin Anthony Pasnik, Cedar Park, TX (US);

Thomas John Tryt, Binghamton, NY (US);

John H. Westermann, Jr., Endicott, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06G 7/62 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.


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