The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

May. 15, 2007
Applicants:

Kevin M Boyd, Poughkeepsie, NY (US);

James a Gallo, Essex Junction, VT (US);

Edward P Higgins, Ripton, VT (US);

Mark L Reath, Red Hook, NY (US);

Barbara L Shiffler, Hinesburg, VT (US);

Justin Wong, South Burlington, VT (US);

Inventors:

Kevin M Boyd, Poughkeepsie, NY (US);

James A Gallo, Essex Junction, VT (US);

Edward P Higgins, Ripton, VT (US);

Mark L Reath, Red Hook, NY (US);

Barbara L Shiffler, Hinesburg, VT (US);

Justin Wong, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01T 23/00 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processing system and method. The processing system includes a processing tool, an electrostatic chuck (ESC) arranged within the processing tool, and a system that at least one of detects at least one of an ESC bias spike and an ESC current spike of the ESC and determines when an ESC bias voltage is zero or exceeds a threshold value. The method includes at least one of detecting at least one of an ESC bias spike and an ESC current spike of the ESC, and determining when an ESC bias voltage is zero or exceeds a threshold value. The system and method can be used in real time ESC and plasma processing diagnostics to minimize yield loss and wafer scrap.


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