The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
May. 19, 2010
Chih-ming Hung, McKinney, TX (US);
Charvaka Duvvury, Plano, TX (US);
Chih-Ming Hung, McKinney, TX (US);
Charvaka Duvvury, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An ESD protection circuit () is guarded by a parallel first precharge elimination circuit () relative to an I/O pad () and a parallel second precharge elimination circuit () relative to a VDD pad (). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode () is connected between I/O pad and VDD. Circuit () is between I/O pad and ground () and is powered by the same VDD. Circuit () includes a first resistor (), a first nMOS transistor (), and a first RC timer including a second resistor () and a first capacitor (). Circuit () includes a third resistor (), a second nMOS transistor (), and a second RC timer including a fourth resistor () and a second capacitor ().
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile