The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Nov. 27, 2007
Applicants:
Anup Nayak, Fremont, CA (US);
Sanjay Kumar Sancheti, Sunnyvale, CA (US);
Shailja Garg, Fremont, CA (US);
Inventors:
Anup Nayak, Fremont, CA (US);
Sanjay Kumar Sancheti, Sunnyvale, CA (US);
Shailja Garg, Fremont, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/74 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
Abstract
A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.