The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Nov. 18, 2008
Man-kyo Jong, Bucheon-si, KR;
Joon-seo Son, Seoul, KR;
Seung-won Lim, Bucheon-si, KR;
O-soeb Jeon, Seoul, KR;
Man-kyo Jong, Bucheon-si, KR;
Joon-seo Son, Seoul, KR;
Seung-won Lim, Bucheon-si, KR;
O-soeb Jeon, Seoul, KR;
Fairchild Korea Semiconductor Ltd., Bucheon, KR;
Abstract
Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.