The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2011
Filed:
Dec. 10, 2009
Shunsuke Toyoshima, Tokyo, JP;
Kazuo Tanaka, Tokyo, JP;
Masaru Iwabuchi, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.