The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

Feb. 04, 2005
Applicants:

Joong Jeon, Cupertino, CA (US);

Takashi Whitney Orimoto, Mountain View, CA (US);

Robert B. Ogle, San Jose, CA (US);

Harpreet Sachar, Milpitas, CA (US);

Wei Zheng, Santa Clara, CA (US);

Inventors:

Joong Jeon, Cupertino, CA (US);

Takashi Whitney Orimoto, Mountain View, CA (US);

Robert B. Ogle, San Jose, CA (US);

Harpreet Sachar, Milpitas, CA (US);

Wei Zheng, Santa Clara, CA (US);

Assignees:

Spansion LLC, Sunnyvale, CA (US);

GLOBALFOUNDRIES, Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.


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