The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2010
Filed:
May. 12, 2006
Vasisht Mantra Vadi, San Jose, CA (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
James M. Simkins, Park City, UT (US);
Vasisht Mantra Vadi, San Jose, CA (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
James M. Simkins, Park City, UT (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.