The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2010
Filed:
Sep. 19, 2007
Gary Moscaluk, Colorado Springs, CO (US);
Gary Moscaluk, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A charge pump circuit has at least three stages: a pre-stage, a common stage and post stage. Each stage has three devices which are common. An NMOS device, which is called the charge injection device (CID), is controlled by a PMOS device during charge injection and an NMOS device during charge trapping. Also, each of the stages includes comparison stages for the CID in order to minimize the bulk to source voltage (Vbs) or bulk to drain voltage (Vbd). This greatly improves efficiency during the charge injection phase. Furthermore, the post-stage includes a comparison stage for the PMOS device since the threshold voltage increases as you increase the number of stages with the bulk tied to VPWR. The PMOS comparison stage should be inserted at the stage where the PMOS device begins to operate in the sub-threshold region, which is technology and voltage dependent.