Esd device layout for effectively reducing internal circuit area and avoiding esd and breakdown damage and effectively protecting high voltage ic

Abstract

An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I/O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.