The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2010

Filed:

Nov. 24, 2008
Applicants:

Hidehito Kitakado, Hyogo, JP;

Masahiko Hayakawa, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Taketomi Asami, Kanagawa, JP;

Inventors:

Hidehito Kitakado, Hyogo, JP;

Masahiko Hayakawa, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Taketomi Asami, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

Channel doping is an effective method for controlling V, but if Vshifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vof both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH, NH, and NO, and a silicon oxynitride film (B) manufactured from SiHand NO. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.


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