The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Feb. 02, 2007
Laurence B. Boucher, Saratoga, CA (US);
Stephen E. J. Blightman, San Jose, CA (US);
Peter K. Craft, San Francisco, CA (US);
David A. Higgen, Saratoga, CA (US);
Clive M. Philbrick, San Jose, CA (US);
Daryl D. Starr, Milpitas, CA (US);
Laurence B. Boucher, Saratoga, CA (US);
Stephen E. J. Blightman, San Jose, CA (US);
Peter K. Craft, San Francisco, CA (US);
David A. Higgen, Saratoga, CA (US);
Clive M. Philbrick, San Jose, CA (US);
Daryl D. Starr, Milpitas, CA (US);
Alacritech, Inc., San Jose, CA (US);
Abstract
A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The TONID also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the TONID to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the TONID as a communication control block (CCB) that can be passed back to the host for message processing by the host. The TONID contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.