The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Jan. 12, 2006
Karl Papadantonakis, Pasadena, CA (US);
Stephanie Chan, Chunglin, TW;
André M. Dehon, Pasadena, CA (US);
Karl Papadantonakis, Pasadena, CA (US);
Stephanie Chan, Chunglin, TW;
André M. DeHon, Pasadena, CA (US);
California Institute of Technology, Pasadena, CA (US);
Abstract
Aggressive pipelining allows Field Programmable Gate Arrays (FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. A reformulation of saturated addition as an associative operation permits a parallel-prefix calculation to be used to perform saturated accumulation at any data rate supported by the device. The method may be extended to other operations containing loops with one or more loop-carried dependencies.