The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
May. 12, 2006
James M. Simkins, Park City, UT (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
James M. Simkins, Park City, UT (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
John M. Thendean, Berkeley, CA (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.