The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7852829 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 14, 2010

Filed:

Jun. 18, 2004
Applicants:

Hung-hsiang Jonathan Chao, Holmdel, NJ (US);

Jinsoo Park, Leonia, NJ (US);

Inventors:

Hung-Hsiang Jonathan Chao, Holmdel, NJ (US);

Jinsoo Park, Leonia, NJ (US);

Assignee:

Polytechnic University, Brooklyn, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Practical packet reassembly in large, multi-plane, multi-stage switches is possible by using a scheduling technique called dynamic packet interleaving. With dynamic packet interleaving scheduling, if more than one packet is contending for the same output link in a switch module, an arbiter in the switch module gives priority to a partial packet (i.e., to a packet that has had at least one cell sent to the queue). The number of reassembly queues required to ensure reassembly is dramatically reduced (e.g., to the number of paths multiplied by the number of scheduling priorities). Deadlock may be avoided by guaranteeing (e.g., reserving) at least one cell space for all partial packets.


Find Patent Forward Citations

Chao, Hung-Hsiang. (2010). Packet reassembly and deadlock avoidance for use in a packet switch (U.S. Patent No. 7852829). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7852829

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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