Semiconductor memory device

Abstract

Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of the gate electrodes and active regions configuring at least any one of the pairs of the transistors, for example, the pair of the transfer transistors are configured obliquely in a predetermined direction from the standard configuration. As a result, a size in a cell outside part including the driver transistor and the transfer transistor is reduced. At the same time, a distance between the load transistors in the central part is reduced as compared with that in the standard configuration. Thus, area reduction in the whole SRAM unit cell is realized.