The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Apr. 28, 2009
Masaki Shiraishi, Hitachinaka, JP;
Noboru Akiyama, Hitachinaka, JP;
Tomoaki Uno, Takasaki, JP;
Nobuyoshi Matsuura, Takasaki, JP;
Masaki Shiraishi, Hitachinaka, JP;
Noboru Akiyama, Hitachinaka, JP;
Tomoaki Uno, Takasaki, JP;
Nobuyoshi Matsuura, Takasaki, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.