The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Apr. 28, 2008
Douglas R. Johnson, Cedar Rapids, IA (US);
James J. Corcoran, Cedar Rapids, IA (US);
Eric J. Danielson, Iowa City, IA (US);
John W. Roltgen, Cedar Rapids, IA (US);
Mark A. Kovalan, Cedar Rapids, IA (US);
Corydon J. Carlson, Cedar Rapids, IA (US);
John L. Persick, Robins, IA (US);
Cleveland C. Gilbert, Cedar Rapids, IA (US);
Samir S. Hemaidan, Cedar Rapids, IA (US);
Shawn M. Stanger, Marion, IA (US);
Douglas R. Johnson, Cedar Rapids, IA (US);
James J. Corcoran, Cedar Rapids, IA (US);
Eric J. Danielson, Iowa City, IA (US);
John W. Roltgen, Cedar Rapids, IA (US);
Mark A. Kovalan, Cedar Rapids, IA (US);
Corydon J. Carlson, Cedar Rapids, IA (US);
John L. Persick, Robins, IA (US);
Cleveland C. Gilbert, Cedar Rapids, IA (US);
Samir S. Hemaidan, Cedar Rapids, IA (US);
Shawn M. Stanger, Marion, IA (US);
Rockwell Collins, Inc., Cedar Rapids, IA (US);
Abstract
A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.