The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Jan. 29, 2009
Applicants:

Vladimir Koifman, Rishon Lezion, IL;

Noam Eshel, Pardesiyya, IL;

Zeituni Golan, Kfar Saba, IL;

Inventors:

Vladimir Koifman, Rishon Lezion, IL;

Noam Eshel, Pardesiyya, IL;

Zeituni Golan, Kfar Saba, IL;

Assignee:

Advasense Technologies Ltd., Ra′Anana, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); G05F 3/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system that includes: multiple transistors that comprise a first transistor that is maintained in a weak inversion state; wherein sources of the multiple transistors are coupled to a low current source; wherein drains of the multiple transistors are coupled to a voltage supply source; a first amplifier that has a positive input, negative input and an output; wherein the positive input receives an input voltage; wherein the negative input is coupled to a source of the first transistor; wherein the output is coupled to a gate of the first transistor and to a multiplication and subtracting circuit; a multiplication and subtraction circuit that is coupled to the first amplifier and outputs an output signal that equals a difference between the input voltage and a product of a current reduction variable and a voltage reduction signal; wherein the voltage reduction signal is associated with a current reduction factor; wherein the output signal is provided to a second transistor that is maintained in weak inversion; and wherein the second transistor outputs, in response to a reception of the output signal, a current that is responsive to the pixel output signal, is proportional to the low current and is inversely proportional to the current reduction variable and the current reduction factor.


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