The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Sep. 19, 2008
Applicants:

Horst Theuss, Wenzenbach, DE;

Markus Loehndorf, Munich, DE;

Florian Schoen, Munich, DE;

Inventors:

Horst Theuss, Wenzenbach, DE;

Markus Loehndorf, Munich, DE;

Florian Schoen, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer-level packaged integrated circuit includes a semiconductor substrate including a first silicon layer. A micro-electromechanical system (MEMS) device is integrated into the first silicon layer. A thin-film deposited sealing member is deposited over the first silicon layer and is configured to seal a cavity in the first silicon layer. At least one additional layer is formed over the sealing member. At least one under bump metallization (UBM) is formed over the at least one additional layer.


Find Patent Forward Citations

Theuss, Horst. (2010). Wafer level packaged mems integrated circuit (U.S. Patent No. 7851925). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7851925

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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