The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Apr. 30, 2007
Applicants:

Ronghua Zhu, Chandler, AZ (US);

Amitava Bose, Tempe, AZ (US);

Vishnu K. Khemka, Phoenix, AZ (US);

Todd C. Roggenbauer, Chandler, AZ (US);

Inventors:

Ronghua Zhu, Chandler, AZ (US);

Amitava Bose, Tempe, AZ (US);

Vishnu K. Khemka, Phoenix, AZ (US);

Todd C. Roggenbauer, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body () including a surface and a transistor source () located in the semiconductor body proximate the surface, and the transistor source includes an area () of alternating conductivity regions (). Another apparatus includes a semiconductor body () including a first conductivity and a transistor source () located in the semiconductor body. The transistor source includes multiple regions () including a second conductivity, wherein the regions and the semiconductor body form an area () of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well () including a first conductivity in a substrate () and implanting a plurality of doped regions () comprising a second conductivity in the semiconductor well. An area () comprising regions of alternating conductivities is then formed in the semiconductor well.


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