The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Feb. 07, 2007
Applicants:

Hideo Yoshino, Chiba, JP;

Hisashi Hasegawa, Chiba, JP;

Inventors:

Hideo Yoshino, Chiba, JP;

Hisashi Hasegawa, Chiba, JP;

Assignee:

Seiko Instruments Inc., Chiba-Shi, Chiba, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.


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