The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Jul. 30, 2008
Yue Fu, Chandler, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Vishnu K. Khemka, Phoenix, AZ (US);
Amitava Bose, Tempe, AZ (US);
Todd C. Roggenbauer, Austin, TX (US);
Yue Fu, Chandler, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Vishnu K. Khemka, Phoenix, AZ (US);
Amitava Bose, Tempe, AZ (US);
Todd C. Roggenbauer, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A dual current path LDMOSFET transistor () is provided which includes a substrate (), a graded buried layer (), an epitaxial drift region () in which a drain region () is formed, a first well region () in which a source region () is formed, a gate electrode () formed adjacent to the source region () to define a first channel region (), and a current routing structure that includes a buried RESURF layer () in ohmic contact with a second well region () formed in a predetermined upper region of the epitaxial layer () so as to be completely covered by the gate electrode (), the current routing structure being spaced apart from the first well region () and from the drain region () on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.