The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2010

Filed:

Mar. 06, 2009
Applicant:

Yoo Nam Jeon, Seongnam-si, KR;

Inventor:

Yoo Nam Jeon, Seongnam-si, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/336 (2006.01); H01L 21/20 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.


Find Patent Forward Citations

Jeon, Yoo. (2010). Method of fabricating semiconductor device (U.S. Patent No. 7851290). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7851290

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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