The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2010
Filed:
May. 09, 2008
Laura S. Chadwick, Essex Junction, VT (US);
James A. Culp, Downingtown, PA (US);
David J Hathaway, Underhill, VT (US);
Anthony D. Polson, Jericho, VT (US);
Laura S. Chadwick, Essex Junction, VT (US);
James A. Culp, Downingtown, PA (US);
David J Hathaway, Underhill, VT (US);
Anthony D. Polson, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.