The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2010
Filed:
Jul. 23, 2007
Stefanos Sidiropoulos, Palo Alto, CA (US);
Don Stark, Palo Alto, CA (US);
Stefanos Sidiropoulos, Palo Alto, CA (US);
Don Stark, Palo Alto, CA (US);
NexLogic Microsystems, Inc., Santa Clara, CA (US);
Abstract
A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.