The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2010

Filed:

Aug. 19, 2008
Applicants:

Michael Bruennert, Munich, DE;

Peter Gregorius, Munich, DE;

Georg Braun, Holzkirchen, DE;

Andreas Gaertner, Munich, DE;

Hermann Ruckerbauer, Moos, DE;

George William Alexander, Durham, NC (US);

Johannes Stecker, Munich, DE;

Inventors:

Michael Bruennert, Munich, DE;

Peter Gregorius, Munich, DE;

Georg Braun, Holzkirchen, DE;

Andreas Gaertner, Munich, DE;

Hermann Ruckerbauer, Moos, DE;

George William Alexander, Durham, NC (US);

Johannes Stecker, Munich, DE;

Assignee:

Qimonda AG, Munich, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.


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