The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7847324 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 07, 2010

Filed:

Dec. 17, 2008
Applicant:

Masaki Kasahara, Tama, JP;

Inventor:

Masaki Kasahara, Tama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.


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Kasahara, Masaki. (2010). Mos transistor and semiconductor integrated circuit (U.S. Patent No. 7847324). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7847324

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