The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2010
Filed:
Nov. 13, 2007
Chai O Chung, Gyeonggi-do, KR;
Jong Min Lee, Gyeonggi-do, KR;
Chan Bae Kim, Gyeonggi-do, KR;
Hyeon Ju an, Gyeonggi-do, KR;
Hyo Seok Lee, Gyeonggi-do, KR;
Sung Kyu Min, Seoul, KR;
Chai O Chung, Gyeonggi-do, KR;
Jong Min Lee, Gyeonggi-do, KR;
Chan Bae Kim, Gyeonggi-do, KR;
Hyeon Ju An, Gyeonggi-do, KR;
Hyo Seok Lee, Gyeonggi-do, KR;
Sung Kyu Min, Seoul, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.