The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2010
Filed:
Aug. 02, 2007
Sung-jun Kim, Hwaseong-si, KR;
Seong-kyu Yun, Seoul, KR;
Chang-ki Hong, Seongnam-si, KR;
Bo-un Yoon, Seoul, KR;
Jong-won Lee, Seongnam-si, KR;
Ho-young Kim, Seongnam-si, KR;
Sung-jun Kim, Hwaseong-si, KR;
Seong-kyu Yun, Seoul, KR;
Chang-ki Hong, Seongnam-si, KR;
Bo-un Yoon, Seoul, KR;
Jong-won Lee, Seongnam-si, KR;
Ho-young Kim, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;
Abstract
Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.