The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2010
Filed:
Feb. 18, 2008
Guenther Hutzl, Bonn, DE;
Stephan Held, Bonn, DE;
Juergen Koehl, Weil im Schoenbuch, DE;
Bernhard Korte, Bonn, DE;
Jens Massberg, Bonn, DE;
Matthias Ringe, Bonn, DE;
Jens Vygen, Bonn, DE;
Guenther Hutzl, Bonn, DE;
Stephan Held, Bonn, DE;
Juergen Koehl, Weil im Schoenbuch, DE;
Bernhard Korte, Bonn, DE;
Jens Massberg, Bonn, DE;
Matthias Ringe, Bonn, DE;
Jens Vygen, Bonn, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.