Semiconductor integrated circuit device and design method thereof

Abstract

In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each row of these dynamic type logic circuit cells is provided, a logic function is allotted to the cells, the number of series connection stages of the cells within an evaluation period determined by a clock cycle of the clock signal is found, and a judgment is made as to whether restrictions can be met by arranging the cells on the semiconductor integrated circuit device and performing delay calculations in a case where the number of series connection stages does not exceed a prescribed number of stages. When the restrictions are met, the whole processing comes to an end. When the restrictions are not met, modifications are made.