Implementing power savings in hss clock-gating circuit

Abstract

A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the Cclocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a Cclock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the Cclocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation.