Pulse output direct digital synthesis circuit

Abstract

A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency f. The clock signal generator generates an output clock signal having a frequency f, wherein fis less than f. A modulo-N counter accepts the reference clock signal as input. The modulo-N counter generates a phase-indication signal of the reference clock. The phase indication signal has N clock phases repeating at a frequency of f/N. An accumulator iteratively accumulates a frequency control word into a modulo-N adder and produces an accumulated value. One or more bits of the accumulated value is fed-back into the modulo-N adder for adding modulo N to the accumulated value in the next iteration. N of the modulo-N adder is the same integer as in the modulo-N counter. A clock edge selector receives as inputs the phase indication signal and one or more bits of the accumulated value and by comparing the inputs selects an edge of the reference clock signal upon which to toggle the state of the output clock signal. The clock edge selector preferably selects the edge from: (i) only rising edges of the reference clock signal, (ii) only falling edges of the reference clock signal or (iii) both rising and falling edges of the reference clock signal. The clock edge selector selects between a rising edge and a falling edge of the reference clock signal preferably based on one or more bits of the accumulated value.