The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2010

Filed:

Apr. 05, 2005
Applicants:

Shimon Muller, Sunnyvale, CA (US);

Ariel Hendel, Cupertino, CA (US);

Yatin Gajjar, Fremont, CA (US);

Michael Wong, Cupertino, CA (US);

Andreas Bechtolsheim, Stanford, CA (US);

David Cheriton, Palo Alto, CA (US);

Mohammad Issa, Los Altos, CA (US);

Aly Orady, Sunnyvale, CA (US);

Raju Penumatcha, Fremont, CA (US);

Inventors:

Shimon Muller, Sunnyvale, CA (US);

Ariel Hendel, Cupertino, CA (US);

Yatin Gajjar, Fremont, CA (US);

Michael Wong, Cupertino, CA (US);

Andreas Bechtolsheim, Stanford, CA (US);

David Cheriton, Palo Alto, CA (US);

Mohammad Issa, Los Altos, CA (US);

Aly Orady, Sunnyvale, CA (US);

Raju Penumatcha, Fremont, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A network system which includes a plurality of separate processing entities, an input output bus, and a network interface unit shared among the plurality of separate processing entities is disclosed. The network interface unit is coupled to the plurality of separate processing entities via the input output bus. The network interface unit has a plurality of memory access channels and each memory access channel is assigned to one processing entity.


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