Method of controlling memory and memory system thereof

Abstract

The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.