The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2010

Filed:

Jan. 29, 2008
Applicants:

Anosh B. Davierwalla, San Diego, CA (US);

Chul Kyu Lee, San Diego, CA (US);

Vannam Dang, San Diego, CA (US);

Inventors:

Anosh B. Davierwalla, San Diego, CA (US);

Chul Kyu Lee, San Diego, CA (US);

Vannam Dang, San Diego, CA (US);

Assignee:

QUALCOMM, Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.


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