Dividing circuit and phase locked loop using the same

Abstract

The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal. The second dividing circuit selects one of the edges of the reference clock signal applied for at least one cycle of the second division signal in response to the selection signal, and synchronizes and generates the second division signal on the basis of the selected edge of the reference clock signal. A synchronous signal output portion is configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage.