The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2010
Filed:
Oct. 28, 2009
Ravindraraj Ramaraju, Round Rock, TX (US);
David R. Bearden, Austin, TX (US);
Cody B. Croxton, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Ravindraraj Ramaraju, Round Rock, TX (US);
David R. Bearden, Austin, TX (US);
Cody B. Croxton, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A multiplexed data flip-flop circuit () is described in which a multiplexer () outputs functional or scan data, a master latch () generates a master latch output signal at a hold time under control of a master clock signal, a slave latch () generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry () generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry () uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.