Reconfigurable array to compute digital algorithms

Abstract

An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is provided on an integrated circuit. The integrated circuit includes a plurality of data inputs, a plurality of data outputs, a plurality of programming inputs and a plurality of logic units arranged as a matrix array. At least some of the logic units each comprise a Boolean logic computational unit having input terminals, output terminals, and programming terminals. The logic units are operated on a clocked basis such that each logic unit is controlled by the programming inputs. Each logic unit comprises a selector coupled to the input terminals and programmable to selectively couple input data from either the data inputs or output terminals of one or more other computational units to the computational unit. An array of programmable interconnects the data inputs of the matrix array and the output terminals of each of the logic units with input terminals of other logic units and to the data outputs of the matrix array. Each of the logic units and each of the selectors and the array of programmable interconnects are operated on a clocked basis such that Boolean functionality is determined during each clock cycle.