The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2010

Filed:

Feb. 14, 2008
Applicants:

Edward C. Cooney, Iii, Jericho, VT (US);

Mark Dupuis, South Burlington, VT (US);

William J. Murphy, North Ferrisburg, VT (US);

Steven S. Williams, Essex Junction, VT (US);

Inventors:

Edward C. Cooney, III, Jericho, VT (US);

Mark Dupuis, South Burlington, VT (US);

William J. Murphy, North Ferrisburg, VT (US);

Steven S. Williams, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/73 (2006.01); H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
Abstract

Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices.


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