The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2010

Filed:

Apr. 04, 2007
Applicants:

Sivakumar Velusamy, Los Gatos, CA (US);

Navaneethan Sundaramoorthy, San Jose, CA (US);

Raj Kumar Nagarajan, San Jose, CA (US);

Satish R. Ganesan, Mountain View, CA (US);

Inventors:

Sivakumar Velusamy, Los Gatos, CA (US);

Navaneethan Sundaramoorthy, San Jose, CA (US);

Raj Kumar Nagarajan, San Jose, CA (US);

Satish R. Ganesan, Mountain View, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to execute a plurality of instructions one or more times. The target processor provides state data at the trace port and to the input port of the bus. A profile circuit arrangement is coupled to the output port of the first bus, and a memory is coupled to the profile circuit arrangement. The profile circuit arrangement is configured to read data from the output port of the first bus and write the data to the memory.


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