The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
Aug. 25, 2004
Pradeep Kathail, Los Altos, CA (US);
Kirk Lougheed, Atherton, CA (US);
David Barach, Boxboro, MA (US);
Philip Winterfield, Palo Alto, CA (US);
Pradeep Kathail, Los Altos, CA (US);
Kirk Lougheed, Atherton, CA (US);
David Barach, Boxboro, MA (US);
Philip Winterfield, Palo Alto, CA (US);
Cisco Technology, Inc., San Jose, CA (US);
Abstract
A router that includes a plurality of processors (SMPs) where there is 'affinity' between particular processors and particular interfaces: Each of the router's interfaces are assigned to one of the processors. A packet arriving at a particular interface will be handled by the processor having an affinity to that particular interface. If the packet's egress is on an interface assigned to the same processor, then the output process will also be handled by that processor. If the egress interface has an affinity to a different processor, then the packet is handed over to the other processor for egress. The data structures that must be retrieved from memory to handle a packet are often associated with the interfaces through which the packet passes. Thus, having a particular processor handle all the packets that pass through a particular interface insures that the data structures needed to handle the packets will more likely be stored in the processor's cache and less likely be the object of inter-processor lock contention.